1. Field of Use
The present invention relates to macrocells and more particularly to flip-flop cells with a scan capability.
2. Prior Art
A well known technique for implementing very large scale integration (VLSI) microprocessor chips is through the use of macro or library cells. The logic designer combines macro cells included in the library corresponding to types of restricted function building blocks (e.g. inverters, flip-flops, selectors) by specifying interconnections between cell inputs and outputs. The patterns of interconnections are included in an interconnection layer of the VLSI microprocessor chip.
In general, the cell/gate array manufacturers specify a set of design rules which must be followed precisely in making such interconnections. One such rule is that there can be no gated clock signals used with synchronous flip-flops. This becomes a problem in implementing those designs which have registers which are loaded only on selected conditions. That is, the register contents do not change on every clock or on every cycle or on every instruction.
Characteristically, LSI chips often or sometimes include some type of diagnostic serial scan capability used in testing and verifying proper system operation. An example of this type of capability is described in U.S Pat. Nos. 3,582,902 and 4,649,539.
In order to implement such a capability using predefined cells, it becomes necessary to interconnect two or more such cells together. For example, it has been proposed to connect a scannable D flip-flop and an input multiplexer cell with another input multiplexer cell positioned before the input multiplexer to accommodate the scan requirement. Also, it has been proposed to interconnect separate inverter, AND/OR and D flip-flop cells together. Alternatively, the scan requirement has been implemented by utilizing a special diagnostic circuit included within a major cell such as in the arrangement described in U.S. Pat. No. 4,575,674.
The above arrangements require additional cells or space for additional interconnects which not only reduce chip area but because of longer signal propagation times, circuit speed is reduced thereby adversely affecting system performance. Additionally, the use of different cells can provide different speeds which vary as a function of the physical locations of the cells within the array. This can lead to less predictable operation and difficulties in processing system conditions.
Accordingly, it is a primary object of the present invention to provide a device which complies with the restrictions imposed by IC manufacturers.
It is further object of the present invention to provide a device which is capable of performing a wide variety of functions but without requiring an increase in area when implemented in an macrocell array.
It is still a further object of the invention to provide a device which requires a minimum signal propagation delay.